On April 16, TSMC Chairman CC Wei addressed competition from Intel’s EMIB packaging in an earnings call, stressing confidence in its large reticle packaging and SoIC integration as superior solutions for customers.

TSMC positions CoWoS as its flagship advanced packaging platform. Monthly CoWoS capacity will reach 115,000–140,000 wafers by late 2026, and surge to roughly 170,000 wafers in 2027. Major expansion is underway in Tainan and Chiayi to meet surging AI and high-performance computing demand.

For next-gen packaging, TSMC is developing CoPoS (Panel-Level Packaging). Key equipment installation finished in February 2026, with full line setup targeted for June. Mass production is expected as early as 2028–2029.

CoPoS uses panel-level processing to exceed traditional size limits, boost throughput per unit area, and lower packaging costs—ideal for next-generation large chips.

Compared with Intel EMIB, TSMC CoWoS already dominates the accelerator ecosystem, powering NVIDIA H100, A100 and other flagship AI chips. CoPoS will extend TSMC’s leadership in ultra-large, high-bandwidth chip integration.

ICgoodFind: TSMC’s technology roadmap and capacity expansion highlight fierce competition in advanced packaging. We track industry innovations and deliver stable component supply chains for global partners.